1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a cell array pattern in one-transistor.one-capacitor type dynamic memory cells.
2. Description of the Related Art
As an arrangement of a dynamic memory cell with a one-transistor.one-capacitor structure in a dynamic memory, various patterns have been proposed to increase the integration density thereof. FIG. 8 schematically shows an example of a conventional cell array pattern of folded bit line type. In FIG. 8, 61 denotes bit lines arranged in parallel with one another, and 62 denotes bit line sense amplifiers arranged on both sides of the bit lines 61. Adjacent two of the bit lines 61 make one complementary pair and are connected to a corresponding one of the bit line sense amplifiers 62. Each of the bit lines 61 has contacts or connection members 63 which are in contact with drain regions (or source regions) of memory cell transistors (charge transfer transistors) at desired pitch P in longitudinal direction thereof. In this case, if desired two bit lines adjacent to each other are noted, a position of a transistor contact 63 in one bit line 61 is deviated by 1/2 pitch in the bit line direction from a position of a transistor contact 63 of an adjacent bit line 61.
FIG. 9 shows part of the cell array pattern of FIG. 8 in detail. In FIG. 9, 61 denotes bit lines, 63 bit line contacts, 71a cell regions having a pattern extending diagonally right and upward, and 71b cell regions having a pattern extending diagonally right and downward, respectively. The two kinds of cell region patterns are alternately arranged every 1/2 pitch in the bit line direction. Further, 72 denotes word lines which are also used as gate electrodes of the cell transistors, 73 denotes capacitor storage electrodes provided for every memory cell, and 74 contacts (capacitor contacts) for connecting source regions 43 or 44 of cell transistors to the capacitor storage electrodes 73, respectively.
The cell regions 71a and 71b have a cross-sectional structure as shown in FIG. 4. In FIG. 4, 41 denotes a semiconductor substrate, 42 denotes a field insulating film for cell isolation selectively formed in the semiconductor substrate 41, 43 and 44 denote source regions of first and second cell transistors which are formed of diffused regions of a conductivity type opposite to that of the semiconductor substrate, 45 denotes a common drain region of the first and second cell transistors which is formed of a diffused region of a conductivity type opposite to that of the semiconductor substrate, and 46 and 47 denote the gate electrodes of the first and second cell transistors which are provided through a thin insulating film 48 above the semiconductor substrate 41 and used as part of the word lines 72. Further, 49 denotes a first interlevel insulator, 61 denotes the bit lines, 63 denotes the transistor contact which is in contact with the drain region 45 through a contact hole. 72 denotes the word lines and 50 denotes a second interlevel insulator.
The first and second cell transistors include a charge storage capacitor, respectively. That is, capacitor storage electrodes denoted by 73 ar partly disposed on the second interlevel insulator 50 so as to be located above part of the upper portion of the bit lines 61, and are in contact with the source regions 43 and 44 of the cell transistors via contact holes, respectively. A capacitor plate electrode 52 is provided so that the capacitor storage electrodes 73 are faced through a thin capacitor insulating film 51, thereby providing a stacked capacitor.
In the above cell array pattern, the bit lines 61 and the word lines 72 are arranged in respective directions to intersect with each other, the cell region 71a or 71b for two cell transistors is provided to cross one of the bit lines 61 and adjacent two of the word lines 72, respectively, each bit line 61 is in contact with the common region of the two cell transistors at the portion intersecting the bit line 61 and the cell region 71a or 71b, the capacitors are connected to the two cell transistors, and the cell regions 71a and 71b are provided with patterns which are inclined in the right-upward and right-downward directions, respectively, and are alternately arranged every 1/2 pitch in the bit line direction.
However, when the cell regions 71a and 71b are provided in this way, it is difficult to increase the integration density of the cell regions. That is, as shown in FIG. 9, the integration density of the cell regions is determined by the minimum distance d0 between the adjacent two patterns having different directions. The minimum distance dx between the adjacent two patterns having the same directions has a large space as compared to the minimum distance d0, thereby creating a uselessly unoccupied area.
As described above, since the conventional dynamic memory cells are provided by alternately arranging two kinds of patterns every 1/2 pitch as the cell regions, it is difficult to increase the integration density of cell regions.